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| SH7604 Datasheet, PDF (548/633 Pages) Hitachi Semiconductor – Hardware Manual | |||
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CKIO
Upper
address
Lower
address
Tp
Trr
BS
CSn
tCSD1
RD/WR,
WE
RD
WEn,
CASxx,
DQMxx
tCASD2
tCASD2
D31âD0
Trc1
Trc2
tCASD2
Tre
tCSD1
DACKn
WAIT
RAS,
CE
tRASD2
tRASD2
tRASD2
CAS,
OE
CKE
Figure 16.46 DRAM CAS-Before-RAS Refresh Cycle
(TRP = 1 Cycle, TRAS = 2 Cycles, PLL On)
532
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