SH7604 Datasheet, PDF (8/633 Pages) Hitachi Semiconductor – Hardware Manual

3.3 Bus Width of the CS0 Area................................................................................................ 62
3.4 Switching between Master Mode and Slave Mode............................................................ 63
Section 4 Exception Handling........................................................................................ 65
4.1 Overview............................................................................................................................ 65
4.1.1 Types of Exception Handling and Priority Order ................................................. 65
4.1.2 Exception Handling Operations............................................................................ 66
4.1.3 Exception Vector Table ........................................................................................ 67
4.2 Resets ................................................................................................................................. 69
4.2.1 Types of Resets ..................................................................................................... 69
4.2.2 Power-On Reset .................................................................................................... 70
4.2.3 Manual Reset ........................................................................................................ 70
4.3 Address Errors.................................................................................................................... 71
4.3.1 Sources of Address Errors .................................................................................... 71
4.3.2 Address Error Exception Handling....................................................................... 72
4.4 Interrupts ............................................................................................................................ 72
4.4.1 Interrupt Sources................................................................................................... 72
4.4.2 Interrupt Priority Levels........................................................................................ 73
4.4.3 Interrupt Exception Handling ............................................................................... 73
4.5 Exceptions Triggered by Instructions ................................................................................ 74
4.5.1 Instruction-Triggered Exception Types................................................................ 74
4.5.2 Trap Instructions ................................................................................................... 74
4.5.3 Illegal Slot Instructions ......................................................................................... 74
4.5.4 General Illegal Instructions................................................................................... 75
4.6 When Exception Sources are Not Accepted ...................................................................... 75
4.6.1 Immediately after a Delayed Branch Instruction.................................................. 75
4.6.2 Immediately after an Interrupt-Disabled Instruction ............................................ 76
4.7 Stack Status after Exception Handling .............................................................................. 76
4.8 Usage Notes ....................................................................................................................... 76
4.8.1 Value of Stack Pointer (SP).................................................................................. 76
4.8.2 Value of Vector Base Register (VBR).................................................................. 76
4.8.3 Address Errors Caused by Stacking of Address Error Exception Handling ........ 77
4.8.4 Manual Reset during Register Access .................................................................. 77
Section 5 Interrupt Controller (INTC) ......................................................................... 79
5.1 Overview............................................................................................................................ 79
5.1.1 Features ................................................................................................................. 79
5.1.2 Block Diagram...................................................................................................... 79
5.1.3 Pin Configuration.................................................................................................. 81
5.1.4 Register Configuration.......................................................................................... 81
5.2 Interrupt Sources................................................................................................................ 82
5.2.1 NMI Interrupt........................................................................................................ 82
5.2.2 User Break Interrupt ............................................................................................. 82
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