SH7604 Datasheet, PDF (153/633 Pages) Hitachi Semiconductor – Hardware Manual

• Bit 11—Area 0 Burst ROM Enable (BSTROM)
Bit 11: BSTROM
0
1
Description
Area 0 is accessed normally
Area 0 is accessed as burst ROM
(Initial value)
• Bit 10—Partial Space Share Specification (PSHR): When bus arbitration is in master mode and
the PSHR bit is 1, only area 2 is handled as a shared space. When areas other than area 2 are
accessed, bus ownership is not requested. When this bit is 1, address monitor specification is
disabled. This mode is called partial-share master mode. The initial value is 0.
• Bits 9 and 8—Long Wait Specification for Areas 2 and 3 (AHLW1, AHLW0): When the basic
memory interface setting is made for area 2 and area 3, the wait specification of this field is
effective when the bits that specify the respective area waits in the wait control register
(W21/W20 or W31/W30) specify long waits (i.e., 11).
Bit 9: AHLW1
0
1
Bit 8: AHLW0
0
1
0
1
Description
3 waits
4 waits
5 waits
6 waits
(Initial value)
• Bits 7 and 6—Long Wait Specification for Area 1 (A1LW1, A1LW0): When the basic
memory interface setting is made for area 1, the wait specification of this field is effective
when the bits that specify the wait in the wait control register specify long wait (i.e., 11).
Bit 7: A1LW1
0
1
Bit 6: A1LW0
0
1
0
1
Description
3 waits
4 waits
5 waits
6 waits
(Initial value)
• Bits 5 and 4—Long Wait Specification for Area 0 (A0LW1, A0LW0): When the basic
memory interface setting is made for area 0, the wait specification of this field is effective
when the bits that specify the wait in the wait control register specify long wait (i.e., 11).
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