SH7604 Datasheet, PDF (331/633 Pages) Hitachi Semiconductor – Hardware Manual

Timer drive
clock
FRC lower-byte write cycle
Address
OCR address
Internal write
signal
FRC
N
N+1
OCR
N
M
Write data
Compare match
signal
Disabled
Figure 11.16 Contention between OCR and Compare Match
5. Internal Clock Switching and Counter Operation
FRC will sometimes begin incrementing because of the timing of switching between internal
clocks. Table 11.4 shows the relationship between internal clock switching timing (CKS1 and
CKS0 bit rewrites) and FRC operation.
When an internal clock is used, the FRC clock is generated when the falling edge of an internal
clock (created by dividing the system clock (φ)) is detected. When a clock is switched to high
before the switching and to low after switching, as shown in case 3 in table 11.4, the
switchover is considered a falling edge and an FRC clock pulse is generated, causing FRC to
increment. FRC may also increment when switching between an internal clock and an external
clock.
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