SH7604 Datasheet, PDF (217/633 Pages) Hitachi Semiconductor – Hardware Manual

When the SH7604 shifts to a read cycle immediately after a write, the write data becomes high
impedance when the clock rises, but the RD signal, which indicates read cycle data output enable,
is not asserted until the clock falls. The result is that no waits are inserted into the access cycle.
When bus arbitration is being performed, an empty cycle is inserted for arbitration, so no wait is
inserted between cycles.
T1
T2 Twait T1 T2 Twait T1
T2
CKIO
A26–A0
CSm
CSn
BS
RD/WR
RD
D31–D0
CSm space read
CSn space read
CSn space write
Specification of waits
Specification of waits
between CSm accesses between CSn accesses
(reading different spaces) (read followed by write)
Figure 7.47 Waits between Access Cycles
7.10 Bus Arbitration
The SH7604 has a bus arbitration function that, when a bus release request is received from an
external device, releases the bus to that device after the bus cycle being executed is completed. In
addition, it also has a bus arbitration function for supporting the connection of two processors.
These are connected to each other as master and slave through bus arbitration, which enables a
multiprocessor system to be implemented with a minimum of hardware.
There are three modes for bus arbitration: master mode, partial-share master mode, and slave
mode. Master mode keeps the bus under normal conditions and permits other devices to use the
bus by releasing it when they request its use. The slave mode normally does not have the bus. The
bus is requested when an external bus access cycle comes up and then releases the bus when the
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