SH7604 Datasheet, PDF (626/633 Pages) Hitachi Semiconductor – Hardware Manual

BSC
Bit
Bit Name
15 RAS precharge time
(TRP)
14 RAS-CAS delay (RCD)
13
12, 11
Write-precharge delay
(TRWL)
CAS-before-RAS
refresh RAS assert time
(TRAS1, TRAS0)
10 Burst enable (BE)
9 Bank active mode (RASD)
Value
0
1
0
1
0
1
00
01
10
11
0
1
0
1
Description
1 cycle (Initial value)
2 cycles
1 cycle (Initial value)
2 cycles
1 cycle (Initial value)
2 cycles
2 cycles (Initial value)
3 cycles
4 cycles
Reserved (setting prohibited)
Burst disabled (Initial value)
High-speed page mode during DRAM interface is
enabled. Data is continuously transferred in static
column mode during pseudo-SRAM interfacing.
During synchronous DRAM access, burst is always
enabled regardless of this bit.
For synchronous DRAM, read or write is performed
using auto-precharge mode.
The next access always starts with a bank active
command.
For synchronous DRAM, access ends with bank
active status. This is only valid for area 3. When
area 2 is synchronous DRAM, the mode is always
auto-precharge.
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