SH7604 Datasheet, PDF (202/633 Pages) Hitachi Semiconductor – Hardware Manual

Tp
Tr
Tc1
Tw
Twx
Tc2
CKIO
A26–A14
A13–A1
RAS
CASn
RD/WR
Read
RD
D31–D0
RD/WR
Write
RD
D31–D0
CS3
BS
WAIT
Figure 7.33 External Wait State Timing
7.6.5 Burst Access
In addition to the ordinary mode of DRAM access, in which row addresses are output at every
access and data is then accessed, DRAM also has a high-speed page mode for use when
continuously accessing the same row that enables fast access of data by changing only the column
address after the row address is output. Select ordinary access or high-speed page mode by setting
the burst enable bit (BE) in MCR. Figure 7.34 shows the timing of burst operation in high-speed
page mode. When performing burst access, cycles can be inserted using the wait state control
function.
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