SH7206 Datasheet, PDF (999/1188 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

Section 21 On-Chip RAM
Section 21 On-Chip RAM
This LSI has an on-chip RAM module which can be used to store instructions or data.
On-chip RAM operation and write access to the RAM can be enabled or disabled through the
RAM enable bits and RAM write enable bits.
21.1 Features
• Pages
The on-chip RAM is divided into four pages (pages 0 to 3).
• Memory map
The on-chip RAM is located in the address spaces shown in table 21.1.
Table 21.1 On-Chip RAM Address Spaces
Page
Page 0
Page 1
Page 2
Page 3
Address
H'FFF80000 to H'FFF87FFF
H'FFF88000 to H'FFF8FFFF
H'FFF90000 to H'FFF97FFF
H'FFF98000 to H'FFF9FFFF
• Ports
Each page has two independent read and write ports and is connected to the internal bus (I
bus), CPU instruction fetch bus (F bus), and CPU memory access bus (M bus). (Note that the F
bus is connected only to the read ports.)
The F bus and M bus are used for access by the CPU, and the I bus is used for access by the
DMAC.
• Priority
When the same page is accessed from different buses simultaneously, the access is processed
according to the priority. The priority is I bus > M bus > F bus.
Rev. 3.00 Jun. 18, 2008 Page 975 of 1160
REJ09B0191-0300