SH7206 Datasheet, PDF (601/1188 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

Section 10 Multi-Function Timer Pulse Unit 2 (MTU2)
TCNT_3
TCNT_4
Buffer transfer-enabled period
Buffer register Data*
Data1
Data2
Temporary register
Data*
Data2
General register
Data*
Data2
Note: * Buffer transfer at the crest is selected.
The skipping count is set to three.
T3AEN is set to 1.
Figure 10.77 Example of Operation when Buffer Transfer is Linked with Interrupt
Skipping (BTE1 = 1 and BTE0 = 0)
Skipping counter 3ACNT 0
1
2
3
0
1
2
3
0
Skipping counter 4VCNT
0
1
2
3
0
1
2
3
Buffer transfer-enabled period
(T3AEN is set to 1)
Buffer transfer-enabled period
(T4VEN is set to 1)
Buffer transfer-enabled period
(T3AEN and T4VEN are set to 1)
Note: * The skipping count is set to three.
Figure 10.78 Relationship between Bits T3AEN and T4VEN in TITCR and Buffer
Transfer-Enabled Period
Rev. 3.00 Jun. 18, 2008 Page 577 of 1160
REJ09B0191-0300