SH7206 Datasheet, PDF (711/1188 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

Section 12 Port Output Enable 2 (POE2)
12.3.7 Port Output Enable Control Register 1 (POECR1)
POECR1 is an 8-bit readable/writable register that controls high-impedance state of the pins.
Bit: 7
6
5
4
3
2
1
0
-
-
-
-
MTU2 MTU2 MTU2 MTU2
PE3ZE PE2ZE PE1ZE PE0ZE
Initial value: 0
0
0
0
0
0
0
0
R/W: R R R R R/W* R/W* R/W* R/W*
Note: * Can be modified only once after a power-on reset.
Bit
Bit Name
7 to 4 —
Initial
Value
All 0
3
MTU2PE3ZE 0
2
MTU2PE2ZE 0
1
MTU2PE1ZE 0
R/W
R
R/W*
R/W*
R/W*
Description
Reserved
These bits are always read as 0. The write value
should always be 0.
MTU2 PE3 High-Impedance Enable
Specifies whether to place the PE3/TIOC0D pin for
channel 0 in the MTU2 in high-impedance state when
either POE8F or MTU2CH0HIZ bit is set to 1.
0: Does not place the pin in high-impedance state
1: Places the pin in high-impedance state
MTU2 PE2 High-Impedance Enable
Specifies whether to place the PE2/TIOC0C pin for
channel 0 in the MTU2 in high-impedance state when
either POE8F or MTU2CH0HIZ bit is set to 1.
0: Does not place the pin in high-impedance state
1: Places the pin in high-impedance state
MTU2 PE1 High-Impedance Enable
Specifies whether to place the PE1/TIOC0B pin for
channel 0 in the MTU2 in high-impedance state when
either POE8F or MTU2CH0HIZ bit is set to 1.
0: Does not place the pin in high-impedance state
1: Places the pin in high-impedance state
Rev. 3.00 Jun. 18, 2008 Page 687 of 1160
REJ09B0191-0300