SH7206 Datasheet, PDF (864/1188 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

Section 17 A/D Converter (ADC)
Table 17.3 Analog Input Channels and ADDR
Analog Input Channel
AN0
AN1
AN2
AN3
AN4
AN5
AN6
AN7
A/D Data Register to Store Conversion Result
A/D0
A/D1
ADDRA_0
ADDRA_1
ADDRB_0
ADDRB_1
ADDRC_0
ADDRC_1
ADDRD_0
ADDRD_1
ADDRE_0
ADDRE_1
ADDRF_0
ADDRF_1
ADDRG_0
ADDRG_1
ADDRH_0
ADDRH_1
17.3.2 A/D Control/Status Register (ADCSR)
ADCSR is a 16-bit readable/writable register that selects the mode, controls the A/D converter,
and enables or disables starting of A/D conversion by external trigger input.
ADCSR is initialized to H'0040 by a power-on reset or in software standby mode or module
standby mode.
Bit: 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
ADF ADIE ADST -
TRGS[3:0]
CKS[1:0]
MDS[2:0]
CH[2:0]
Initial value: 0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
R/W: R/(W)* R/W R/W R R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Note: * Only 0 can be written to clear the flag after 1 is read.
Rev. 3.00 Jun. 18, 2008 Page 840 of 1160
REJ09B0191-0300