SH7206 Datasheet, PDF (242/1188 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

Section 8 Bus State Controller (BSC)
Initial
Bit
Bit Name Value R/W Description
5 to 2 
All 0
R
Reserved
1, 0
HW[1:0]
00
These bits are always read as 0. The write value
should always be 0.
R/W Delay Cycles from RD, WEn Negation to Address, CS0
Negation
Specify the number of delay cycles from RD and WEn
negation to address and CS0 negation.
00: 0.5 cycles
01: 1.5 cycles
10: 2.5 cycles
11: 3.5 cycles
Note: * To connect the burst ROM to the CS0 space and switch to burst ROM interface after
activation, set the TYPE[2:0] bits in CS0BCR after setting the burst number by the bits
20 and 21 and the burst wait cycle number by the bits 16 and 17. Do not write 1 to the
reserved bits other than above bits.
Rev. 3.00 Jun. 18, 2008 Page 218 of 1160
REJ09B0191-0300