SH7206 Datasheet, PDF (12/1188 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

5.9.1 Handling Interrupt Request Signals as Sources for CPU Interrupt but Not
DMAC Activating ................................................................................................ 155
5.9.2 Handling Interrupt Request Signals as Sources for Activating DMAC but
Not CPU Interrupt................................................................................................. 155
5.10 Usage Note......................................................................................................................... 156
5.10.1 Timing to Clear an Interrupt Source ..................................................................... 156
5.10.2 Timing of IRQOUT Negation............................................................................... 156
Section 6 User Break Controller (UBC)............................................................ 157
6.1 Features.............................................................................................................................. 157
6.2 Input/Output Pin ................................................................................................................ 159
6.3 Register Descriptions......................................................................................................... 160
6.3.1 Break Address Register (BAR)............................................................................. 161
6.3.2 Break Address Mask Register (BAMR) ............................................................... 162
6.3.3 Break Data Register (BDR) .................................................................................. 163
6.3.4 Break Data Mask Register (BDMR)..................................................................... 164
6.3.5 Break Bus Cycle Register (BBR) ......................................................................... 165
6.3.6 Break Control Register (BRCR) ........................................................................... 167
6.4 Operation ........................................................................................................................... 170
6.4.1 Flow of the User Break Operation ........................................................................ 170
6.4.2 Break on Instruction Fetch Cycle ......................................................................... 172
6.4.3 Break on Data Access Cycle................................................................................. 173
6.4.4 Value of Saved Program Counter ......................................................................... 174
6.4.5 Usage Examples.................................................................................................... 175
6.5 Usage Notes ....................................................................................................................... 178
Section 7 Cache ................................................................................................. 179
7.1 Features.............................................................................................................................. 179
7.1.1 Cache Structure..................................................................................................... 179
7.2 Register Descriptions......................................................................................................... 182
7.2.1 Cache Control Register 1 (CCR1) ........................................................................ 182
7.2.2 Cache Control Register 2 (CCR2) ........................................................................ 184
7.3 Operation ........................................................................................................................... 188
7.3.1 Searching Cache ................................................................................................... 188
7.3.2 Read Access.......................................................................................................... 190
7.3.3 Prefetch Operation (Only for Operand Cache) ..................................................... 190
7.3.4 Write Operation (Only for Operand Cache) ......................................................... 191
7.3.5 Write-Back Buffer (Only for Operand Cache) ..................................................... 191
7.3.6 Coherency of Cache and External Memory.......................................................... 193
7.4 Memory-Mapped Cache .................................................................................................... 194
Rev. 3.00 Jun. 18, 2008 Page xii of xxiv