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SH7206 Datasheet, PDF (692/1188 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series | |||
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Section 12 Port Output Enable 2 (POE2)
12.1 Features
⢠Each of the POE0 to POE8 input pins can be set for falling edge, PÏ/8 à 16, PÏ/16 à 16, or
PÏ/128 Ã 16 low-level sampling.
⢠High-current pins and the pins for channel 0 of the MTU2 can be placed in high-impedance
state by POE0 to POE8 pin falling-edge or low-level sampling.
⢠High-current pins can be placed in high-impedance state when the high-current pin output
levels are compared and simultaneous active-level output continues for one cycle or more.
⢠High-current pins and the pins for channel 0 of the MTU2 can be placed in high-impedance
state by modifying the POE2 register settings.
⢠Interrupts can be generated by input-level sampling or output-level comparison results.
The POE2 has input level detection circuits, output level comparison circuits, and a high-
impedance request/interrupt request generating circuit as shown in the block diagram of figure
12.1.
Rev. 3.00 Jun. 18, 2008 Page 668 of 1160
REJ09B0191-0300
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