SH7206 Datasheet, PDF (509/1188 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

Section 10 Multi-Function Timer Pulse Unit 2 (MTU2)
10.3.21 Timer Output Control Register 2 (TOCR2)
TOCR2 is an 8-bit readable/writable register that controls output level inversion of PWM output
in complementary PWM mode and reset-synchronized PWM mode.
Bit: 7
6
5
4
3
2
1
0
BF[1:0] OLS3N OLS3P OLS2N OLS2P OLS1N OLS1P
Initial value: 0
0
0
0
0
0
0
0
R/W: R/W R/W R/W R/W R/W R/W R/W R/W
Initial
Bit
Bit Name value R/W Description
7, 6 BF[1:0]
00
R/W TOLBR Buffer Transfer Timing Select
These bits select the timing for transferring data from
TOLBR to TOCR2.
For details, see table 10.32.
5
OLS3N
0
R/W Output Level Select 3N*
This bit selects the output level on TIOC4D in reset-
synchronized PWM mode/complementary PWM mode.
See table 10.33.
4
OLS3P
0
R/W Output Level Select 3P*
This bit selects the output level on TIOC4B in reset-
synchronized PWM mode/complementary PWM mode.
See table 10.34.
3
OLS2N
0
R/W Output Level Select 2N*
This bit selects the output level on TIOC4C in reset-
synchronized PWM mode/complementary PWM mode.
See table 10.35.
2
OLS2P
0
R/W Output Level Select 2P*
This bit selects the output level on TIOC4A in reset-
synchronized PWM mode/complementary PWM mode.
See table 10.36.
1
OLS1N
0
R/W Output Level Select 1N*
This bit selects the output level on TIOC3D in reset-
synchronized PWM mode/complementary PWM mode.
See table 10.37.
Rev. 3.00 Jun. 18, 2008 Page 485 of 1160
REJ09B0191-0300