SH7206 Datasheet, PDF (736/1188 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

Section 14 Watchdog Timer (WDT)
Figure 14.1 shows a block diagram of the WDT.
Standby
cancellation
Interrupt
request
WDTOVF
Internal reset
request*
Standby
control
Interrupt
control
Reset
control
WDT
WRCSR
Clock selection
Divider
Clock selector
Overflow
Clock
WTCSR
WTCNT
Standby
mode
Peripheral
clock
Bus interface
[Legend]
WTCSR:
WTCNT:
WRCSR:
Watchdog timer control/status register
Watchdog timer counter
Watchdog reset control/status register
Note: * The internal reset signal can be generated by making a register setting.
Figure 14.1 Block Diagram of WDT
Rev. 3.00 Jun. 18, 2008 Page 712 of 1160
REJ09B0191-0300