SH7206 Datasheet, PDF (390/1188 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

Section 9 Direct Memory Access Controller (DMAC)
9.3.2 DMA Destination Address Registers (DAR)
The DMA destination address registers (DAR) are 32-bit readable/writable registers that specify
the destination address of a DMA transfer. During a DMA transfer, these registers indicate the
next destination address. When the data of an external device with DACK is transferred in single
address mode, DAR is ignored.
To transfer data in word (2-byte), longword (4-byte), or 16-byte unit, specify the address with 2-
byte, 4-byte, or 16-byte address boundary respectively.
DAR is initialized to H'00000000 by a power-on reset and retains the value in manual reset,
software standby mode, and module standby mode.
Bit:
Initial value:
R/W:
31
-
0
R/W
30
-
0
R/W
29
-
0
R/W
28
-
0
R/W
27
-
0
R/W
26
-
0
R/W
25
-
0
R/W
24
-
0
R/W
23
-
0
R/W
22
-
0
R/W
21
-
0
R/W
20
-
0
R/W
19
-
0
R/W
18
-
0
R/W
17
-
0
R/W
16
-
0
R/W
Bit:
Initial value:
R/W:
15
-
0
R/W
14
-
0
R/W
13
-
0
R/W
12
-
0
R/W
11
-
0
R/W
10
-
0
R/W
9
-
0
R/W
8
-
0
R/W
7
-
0
R/W
6
-
0
R/W
5
-
0
R/W
4
-
0
R/W
3
-
0
R/W
2
-
0
R/W
1
-
0
R/W
0
-
0
R/W
Rev. 3.00 Jun. 18, 2008 Page 366 of 1160
REJ09B0191-0300