SH7206 Datasheet, PDF (869/1188 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

Section 17 A/D Converter (ADC)
17.4 Operation
The A/D converter uses the successive-approximation method, and the resolution is 10 bits. It has
three operating modes: single mode, multi mode, and scan mode. Switching the operating mode or
analog input channels must be done while the ADST bit in ADCSR is 0 to prevent incorrect
operation. The ADST bit can be set at the same time as the operating mode or analog input
channels are changed.
17.4.1 Single Mode
Single mode should be selected when only A/D conversion on one channel is required.
In single mode, A/D conversion is performed once for the specified one analog input channel, as
follows:
1. A/D conversion for the selected channel starts when the ADST bit in ADCSR is set to 1 by
software, MTU2, MTU2S, or external trigger input.
2. When A/D conversion is completed, the A/D conversion result is transferred to the A/D data
register corresponding to the channel.
3. After A/D conversion has completed, the ADF bit in ADCSR is set to 1. If the ADIE bit is set
to 1 at this time, an ADI interrupt request is generated.
4. The ADST bit that remains 1 during A/D conversion is automatically cleared to 0 when A/D
conversion is completed, and the A/D converter becomes idle.
When the operating mode or analog input channel selection must be changed during A/D
conversion, to prevent incorrect operation, first clear the ADST bit to 0 to halt A/D conversion.
After making the necessary changes, set the ADST bit to 1 to start A/D conversion again. The
ADST bit can be set at the same time as the mode or channel selection is switched.
Typical operations when a single channel (AN1) is selected in single mode are described next.
Figure 17.2 shows a timing diagram for this example (the bits which are set in this example belong
to ADCSR).
1. Single mode is selected, input channel AN1 is selected (CH[2:0] = 001), the A/D interrupt is
enabled (ADIE = 1), and A/D conversion is started (ADST = 1).
2. When A/D conversion is completed, the A/D conversion result is transferred into ADDRB_0.
At the same time the ADF flag is set to 1, the ADST bit is cleared to 0, and the A/D converter
becomes idle.
3. Since ADF = 1 and ADIE = 1, an ADI0 interrupt is requested.
4. The A/D interrupt handling routine starts.
Rev. 3.00 Jun. 18, 2008 Page 845 of 1160
REJ09B0191-0300