SH7206 Datasheet, PDF (189/1188 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

Section 6 User Break Controller (UBC)
6.3.5 Break Bus Cycle Register (BBR)
BBR is a 16-bit readable/writable register, which specifies (1) disabling or enabling of user break
interrupt requests, (2) including or excluding of the data bus value, (3) bus master of the I bus, (4)
C bus cycle or I bus cycle, (5) instruction fetch or data access, (6) read or write, and (7) operand
size as the break conditions. BBR is initialized to H'0000 by a power-on reset, but retains its
previous value by a manual reset or in software standby mode or sleep mode.
Bit: 15
-
Initial value: 0
R/W: R
14 13 12 11
-
UBID DBE
-
0
0
0
0
R R/W R/W R
10 9
8
7
6
5
4
3
2
1
0
-
CP[1:0]
CD[1:0]
ID[1:0]
RW[1:0]
SZ[1:0]
0
0
0
0
0
0
0
0
0
0
0
R R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Bit
15, 14
Bit Name

13
UBID
12
DBE
11, 10 
9, 8
CP[1:0]
Initial
Value
All 0
0
0
All 0
00
R/W Description
R
Reserved
These bits are always read as 0. The write value
should always be 0.
R/W User Break Interrupt Disable
Disables or enables user break interrupt requests
when a break condition is satisfied.
0: User break interrupt requests enabled
1: User break interrupt requests disabled
R/W Data Break Enable
Selects whether the data bus condition is included in
the break conditions.
0: Data bus condition is not included in break
conditions
1: Data bus condition is included in break conditions
R
Reserved
These bits are always read as 0. The write value
should always be 0.
R/W I-Bus Bus Master Select
Select the bus master when the bus cycle of the break
condition is the I bus cycle. However, when the C bus
cycle is selected, this bit is invalidated (only the CPU
cycle).
x1: CPU cycle is included in break conditions
1x: DMAC cycle is included in break conditions
Rev. 3.00 Jun. 18, 2008 Page 165 of 1160
REJ09B0191-0300