SH7206 Datasheet, PDF (117/1188 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

Section 4 Exception Handling
4.2 Resets
4.2.1 Input/Output Pins
Table 4.5 shows the reset-related pin configuration.
Table 4.5 Pin Configuration
Pin Name
Symbol
Power-on reset RES
I/O
Input
Manual reset MRES Input
Function
When this pin is driven low, this LSI shifts to the power-
on reset processing
When this pin is driven low, this LSI shifts to the manual
reset processing.
4.2.2 Types of Reset
A reset is the highest-priority exception handling source. There are two kinds of reset, power-on
and manual. As shown in table 4.6, the CPU state is initialized in both a power-on reset and a
manual reset. On-chip peripheral module registers are initialized by a power-on reset, but not by a
manual reset.
Table 4.6 Reset States
Conditions for Transition to Reset State
Internal States
Type
WDT
RES H-UDI Command MRES Overflow CPU
On-Chip
WRCSR of
Peripheral
WDT, FRQCR of
Modules, I/O Port CPG
Power-on Low —
—
—
reset
High H-UDI reset assert —
—
command is set
Initialized Initialized
Initialized Initialized
Initialized
Initialized
High Command other —
than H-UDI reset
assert is set
Power-on Initialized Initialized
reset
Not initialized
Manual High Command other Low —
reset
than H-UDI reset
assert is set
Initialized Not initialized* Not initialized
Note:
High Command other
than H-UDI reset
assert is set
High
Manual
reset
Initialized Not initialized*
* The BN bit in IBNR of the INTC is initialized.
Not initialized
Rev. 3.00 Jun. 18, 2008 Page 93 of 1160
REJ09B0191-0300