SH7206 Datasheet, PDF (923/1188 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

Section 19 Pin Function Controller (PFC)
Initial
Bit
Bit Name Value R/W Description
0
PC0MD
0/1*
R/W PC0 Mode
Select the function of the PC0/A0 pin.
• Area 0: 32-bit mode
0: PC0 I/O (port) (initial value)
1: A0 output (address)
• Area 0: 16-bit mode
0: PC0 I/O (port) (initial value)
1: A0 output (address)
• Area 0: 8-bit mode
0: Setting prohibited
1: A0 output (address) (initial value)
Note: * The initial value depends on the operating mode of the LSI.
19.2.7 Port D I/O Registers H, L (PDIORH, PDIORL)
PDIORH and PDIORL are 16-bit readable/writable registers that are used to set the pins on port D
as inputs or outputs. Bits PD31IOR to PD8IOR correspond to pins PD31/D31/ADTRG/TIOC3AS
to PD8/D8/TIOC3AS. PDIORH and PDIORL are enabled when the port D pins are functioning as
general-purpose inputs/outputs (PD31 to PD8) or the TIOC pin is functioning as inputs/outputs of
MTU2S. In other states, they are disabled. A given pin on port D will be an output pin if the
corresponding bit in PDIORH or PDIORL is set to 1, and an input pin if the bit is cleared to 0.
Bits 7 and 0 of PDIORL are reserved. These bits are always read as 0. The write value should
always be 0.
PDIORH and PDIORL are initialized to H'0000 by a power-on; however, the registers are not
initialized by a manual reset or in sleep mode or software standby mode.
(1) Port D I/O Register H (PDIORH)
Bit:
Initial value:
R/W:
15
PD31
IOR
0
R/W
14
PD30
IOR
0
R/W
13
PD29
IOR
0
R/W
12
PD28
IOR
0
R/W
11
PD27
IOR
0
R/W
10
PD26
IOR
0
R/W
9
PD25
IOR
0
R/W
8
PD24
IOR
0
R/W
7
PD23
IOR
0
R/W
6
PD22
IOR
0
R/W
5
PD21
IOR
0
R/W
4
PD20
IOR
0
R/W
3
PD19
IOR
0
R/W
2
PD18
IOR
0
R/W
1
PD17
IOR
0
R/W
0
PD16
IOR
0
R/W
Rev. 3.00 Jun. 18, 2008 Page 899 of 1160
REJ09B0191-0300