SH7206 Datasheet, PDF (216/1188 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

Section 7 Cache
A (31 to 4) Longword 0 Longword 1 Longword 2 Longword 3
A (31 to 4):
Physical address written to external memory (upper three bits are 0)
Longword 0 to 3: One line of cache data to be written to external memory
Figure 7.3 Write-Back Buffer Configuration
Operations in sections 7.3.2 to 7.3.5 are compiled in table 7.8.
Table 7.8 Cache Operations
Cache
Instruction
cache
Operand
cache
Hit/
CPU Cycle Miss
Instruction Hit
fetch
Miss
Prefetch/
read
Hit
Miss
Write-Back Mode/
Write-Through U
Mode
Bit
External Memory
Accession
(through Internal Bus)

 Not generated
Cache Contents
Not renewed


Either mode is
x
available
Write-through

mode
Write-back mode 0
1
Cache renewal cycle is
generated
Not generated
Renewed to new values by
cache renewal cycle
Not renewed
Cache renewal cycle is
generated
Renewed to new values by
cache renewal cycle
Cache renewal cycle is
generated
Renewed to new values by
cache renewal cycle
Cache renewal cycle is
Renewed to new values by
generated. Succeedingly
cache renewal cycle
write-back cycle in write-back
buffer is generated.
Rev. 3.00 Jun. 18, 2008 Page 192 of 1160
REJ09B0191-0300