SH7206 Datasheet, PDF (265/1188 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

Bit
12
11, 10
9
8, 7
6, 5
Section 8 Bus State Controller (BSC)
Bit Name

Initial
Value
0
WTRCD[1:0]* 01

0
A3CL[1:0] 10

All 0
R/W
R
R/W
R
R/W
R
Description
Reserved
This bit is always read as 0. The write value should
always be 0.
Number of Wait Cycles between ACTV Command and
READ(A)/WRIT(A) Command
Specify the minimum number of wait cycles from
issuing the ACTV command to issuing the
READ(A)/WRIT(A) command. The setting for areas 2
and 3 is common.
00: No cycle
01: 1 cycle
10: 2 cycles
11: 3 cycles
Reserved
This bit is always read as 0. The write value should
always be 0.
CAS Latency for Area 3
Specify the CAS latency for area 3.
00: 1 cycle
01: 2 cycles
10: 3 cycles
11: 4 cycles
Reserved
These bits are always read as 0. The write value
should always be 0.
Rev. 3.00 Jun. 18, 2008 Page 241 of 1160
REJ09B0191-0300