SH7206 Datasheet, PDF (448/1188 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

Section 10 Multi-Function Timer Pulse Unit 2 (MTU2)
10.3.1 Timer Control Register (TCR)
The TCR registers are 8-bit readable/writable registers that control the TCNT operation for each
channel. The MTU2 has a total of eight TCR registers, one each for channels 0 to 4 and three
(TCRU_5, TCRV_5, and TCRW_5) for channel 5. TCR register settings should be conducted
only when TCNT operation is stopped.
Bit: 7
6
5
CCLR[2:0]
Initial value: 0
0
0
R/W: R/W R/W R/W
4
3
CKEG[1:0]
0
0
R/W R/W
2
1
0
TPSC[2:0]
0
0
0
R/W R/W R/W
Bit
Bit Name
7 to 5 CCLR[2:0]
Initial
Value
000
4, 3 CKEG[1:0] 00
2 to 0 TPSC[2:0] 000
[Legend]
x: Don't care
R/W
R/W
R/W
R/W
Description
Counter Clear 0 to 2
These bits select the TCNT counter clearing source.
See tables 10.4 and 10.5 for details.
Clock Edge 0 and 1
These bits select the input clock edge. When the input
clock is counted using both edges, the input clock
period is halved (e.g. Pφ/4 both edges = Pφ/2 rising
edge). If phase counting mode is used on channels 1
and 2, this setting is ignored and the phase counting
mode setting has priority. Internal clock edge selection
is valid when the input clock is Pφ/4 or slower. When
Pφ/1, or the overflow/underflow of another channel is
selected for the input clock, although values can be
written, counter operation compiles with the initial value.
00: Count at rising edge
01: Count at falling edge
1x: Count at both edges
Time Prescaler 0 to 2
These bits select the TCNT counter clock. The clock
source can be selected independently for each channel.
See tables 10.6 to 10.9 for details.
Rev. 3.00 Jun. 18, 2008 Page 424 of 1160
REJ09B0191-0300