SH7206 Datasheet, PDF (352/1188 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

Section 8 Bus State Controller (BSC)
Th
T1
Tw
T2
Tf
CKIO
A25 to A0
CSn
WEn
Read
RD/WR
RD
D31 to D0
Write
RD/WR
RD
High
D31 to D0
BS
DACKn*
Note: * The waveform for DACKn is when active low is specified.
Figure 8.39 Wait Timing for SRAM with Byte Selection (BAS = 1)
(SW[1:0] = 01, WR[3:0] = 0001, HW[1:0] = 01)
Rev. 3.00 Jun. 18, 2008 Page 328 of 1160
REJ09B0191-0300