SH7206 Datasheet, PDF (1026/1188 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

Section 23 High-Performance User Debugging Interface (H-UDI)
23.4.2 Reset Configuration
Table 23.4 Reset Configuration
ASEMD*¹
RES
TRST
Chip State
H
L
L
Power-on reset and H-UDI reset
H
Power-on reset
H
L
H-UDI reset only
H
Normal operation
L
L
L
Reset hold*²
H
Power-on reset
H
L
H-UDI reset only
H
Normal operation
Notes: 1. Performs normal mode and ASE mode settings
ASEMD = H, normal mode
ASEMD = L, ASE mode
2. In ASE mode, reset hold is entered if the TRST pin is driven low while the RES pin is
negated. In this state, the CPU does not start up. When TRST is driven high, H-UDI
operation is enabled, but the CPU does not start up. The reset hold state is cancelled
by a power-on reset.
23.4.3 TDO Output Timing
The initial value of the TDO change timing is to perform data output from the TDO pin on the
TCK falling edge. However, setting a TDO change timing switch command in SDIR via the H-
UDI pin and passing the Update-IR state synchronizes the TDO change timing to the TCK rising
edge. Hereafter, to synchronize the change timing of TD0 to the falling edge of TCK, the TRST
pin must be simultaneously asserted with the power-on reset. In a case of power-on reset by the
RES pin, the sync reset is still in operation for a certain period in the LSI even after the RES pin is
negated. Thus, if the TRST pin is asserted immediately after the negate of the RES pin, the TD0
change timing switch command is cleared, resulting the TD0 change timing synchronized with the
falling edge of TCK. To prevent this, make sure to put a period of 20 times of tcyc or longer
between the signal change timing of the RES and TRST pins.
Rev. 3.00 Jun. 18, 2008 Page 1002 of 1160
REJ09B0191-0300