SH7206 Datasheet, PDF (875/1188 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

Section 17 A/D Converter (ADC)
6. The ADST bit is not cleared automatically, so steps 2. to 4. are repeated as long as the ADST
bit remains set to 1. When steps 2. to 4. are repeated, the ADF flag is kept to 1. When the
ADST bit is cleared to 0, A/D conversion stops. The ADF bit is cleared by reading ADF while
ADF = 1, then writing 0 to the ADF bit.
If both the ADF flag and ADIE bit are set to 1 while steps 2. to 4. are repeated, an ADI0 interrupt
is requested at all times. To generate an interrupt on completing conversion of the third channel,
clear the ADF bit to 0 after an interrupt is requested.
Rev. 3.00 Jun. 18, 2008 Page 851 of 1160
REJ09B0191-0300