SH7206 Datasheet, PDF (383/1188 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

Section 9 Direct Memory Access Controller (DMAC)
Figure 9.1 shows the block diagram of the DMAC.
On-chip
memory
On-chip
peripheral module
Iteration
control
Register
control
DMA transfer request signal
DMA transfer acknowledge signal
Interrupt controller
Start-up
control
HEIn
DEIn
Request
priority
control
External ROM
External RAM
External device
(memory mapped)
External device
(with acknowledge)
Bus
interface
Bus state
controller
RDMATCR_n
DMATCR_n
RSAR_n
SAR_n
RDAR_n
DAR_n
CHCR_n
DMAOR
DMARS0
to DMARS3
DMAC module
DREQ0 to DREQ3
DACK0 to DACK3,
TEND0, TEND1
[Legend]
RDMATCR: DMA reload transfer count register
DMATCR: DMA transfer count register
RSAR: DMA reload source address register
SAR:
DMA source address register
RDAR:
DAR:
DMA reload destination address register
DMA destination address register
CHCR:
DMA channel control register
DMAOR:
DMA operation register
DMARS0 to DMARS3: DMA extension resource selectors 0 to 3
HEIn:
DMA transfer half-end interrupt request to the CPU
DEIn:
DMA transfer end interrupt request to the CPU
n = 0 to 7
Figure 9.1 Block Diagram of DMAC
Rev. 3.00 Jun. 18, 2008 Page 359 of 1160
REJ09B0191-0300