SH7206 Datasheet, PDF (320/1188 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

Section 8 Bus State Controller (BSC)
In this LSI, wait cycles can be inserted by specifying each bit in CS3WCR to connect the SDRAM
in variable frequencies. Figure 8.19 shows an example in which wait cycles are inserted. The
number of cycles from the Tr cycle where the ACTV command is output to the Tc1 cycle where
the READ command is output can be specified using the WTRCD1 and WTRCD0 bits in
CS3WCR. If the WTRCD1 and WTRCD0 bits specify one cycles or more, a Trw cycle where the
NOT command is issued is inserted between the Tr cycle and Tc1 cycle. The number of cycles
from the Tc1 cycle where the READ command is output to the Td1 cycle where the read data is
latched can be specified for the CS2 and CS3 spaces independently, using the A2CL1 and A2CL0
bits in CS2WCR or the A3CL1 and A3CL0 bits in CS3WCR and WTRCD0 bit in CS3WCR. The
number of cycles from Tc1 to Td1 corresponds to the SDRAM CAS latency. The CAS latency for
the SDRAM is normally defined as up to three cycles. However, the CAS latency in this LSI can
be specified as 1 to 4 cycles. This CAS latency can be achieved by connecting a latch circuit
between this LSI and the SDRAM.
A Tde cycle is an idle cycle required to transfer the read data into this LSI and occurs once for
every burst read or every single read.
Rev. 3.00 Jun. 18, 2008 Page 296 of 1160
REJ09B0191-0300