SH7206 Datasheet, PDF (1177/1188 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

Index
Numerics
16-bit/32-bit displacement ........................ 39
A
A/D conversion time
(multi mode and scan mode)................... 855
A/D conversion time (single mode)........ 854
A/D conversion timing ........................... 854
A/D converter (ADC) ............................. 835
A/D converter activation......................... 597
A/D converter characteristics................ 1126
A/D converter start request delaying
function................................................... 579
A/D trigger input timing ....................... 1121
Absolute address....................................... 39
Absolute address accessing....................... 39
Absolute maximum ratings................... 1067
AC characteristics................................. 1073
AC characteristics measurement
conditions ............................................. 1125
Access size and data alignment .............. 264
Access wait control................................. 272
Address array.................................. 180, 194
Address array read .................................. 194
Address errors........................................... 97
Address map ........................................... 204
Address multiplexing.............................. 283
Address-array write
(associative operation) ............................ 195
Address-array write
(non-associative operation)..................... 194
Addressing modes..................................... 40
Analog input pin ratings ......................... 860
Arithmetic operation instructions ............. 58
Auto-refreshing....................................... 310
Auto-request mode ................................. 387
B
Bank active ............................................. 303
Banked register and input/output of
banks ....................................................... 150
Bit manipulation instructions .................... 66
Bit synchronous circuit ........................... 830
Block diagram............................................. 7
Branch instructions ................................... 63
Break detection and processing............... 788
Break on data access cycle...................... 173
Break on instruction fetch cycle.............. 172
Burst mode.............................................. 400
Burst MPX-I/O interface......................... 337
Burst read................................................ 295
Burst ROM (clocked asynchronous)
interface .................................................. 323
Burst ROM (clocked synchronous)
interface .................................................. 342
Burst write............................................... 300
Bus arbitration......................................... 350
Bus state controller (BSC) ...................... 199
Bus timing............................................. 1080
Bus-released state...................................... 68
C
Cache ...................................................... 179
Calculating exception handling vector
table addresses .......................................... 92
Canceling software standby mode
(WDT)..................................................... 720
Cascaded operation ................................. 514
Caution on period setting ........................ 612
Changing the division ratio ....................... 84
Changing the frequency .................... 83, 721
Changing the multiplication rate............... 83
Clock frequency control circuit................. 71
Rev. 3.00 Jun. 18, 2008 Page 1153 of 1160
REJ09B0191-0300