SH7206 Datasheet, PDF (824/1188 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

Section 16 I²C Bus Interface 3 (IIC3)
16.3.3 I²C Bus Mode Register (ICMR)
ICMR is an 8-bit readable/writable register that selects whether the MSB or LSB is transferred
first, performs master mode wait control, and selects the transfer bit count.
ICMR is initialized to H'38 by a power-on reset. Bits BC[2:0] are initialized to H'0 by the IICRST
bit in ICCR2.
Bit: 7
6
5
4
3
2
1
0
MLS
-
-
- BCWP
BC[2:0]
Initial value: 0
0
1
1
1
0
0
0
R/W: R/W R R R R/W R/W R/W R/W
Initial
Bit
Bit Name Value R/W Description
7
MLS
0
R/W MSB-First/LSB-First Select
0: MSB-first
1: LSB-first
Set this bit to 0 when the I²C bus format is used.
6

0
R Reserved
This bit is always read as 0. The write value should
always be 0.
5, 4

All 1
R Reserved
These bits are always read as 1. The write value should
always be 1.
3
BCWP
1
R/W BC Write Protect
Controls the BC[2:0] modifications. When modifying the
BC[2:0] bits, this bit should be cleared to 0. In clocked
synchronous serial mode, the BC[2:0] bits should not
be modified.
0: When writing, values of the BC[2:0] bits are set.
1: When reading, 1 is always read.
When writing, settings of the BC[2:0] bits are invalid.
Rev. 3.00 Jun. 18, 2008 Page 800 of 1160
REJ09B0191-0300