SH7206 Datasheet, PDF (76/1188 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

Section 2 CPU
Operation
Classification Types Code
Function
System
control
14
CLRT
T bit clear
CLRMAC MAC register clear
LDBANK Register restoration from specified register
bank entry
LDC
Load to control register
LDS
Load to system register
NOP
No operation
RESBANK Register restoration from register bank
RTE
Return from exception handling
SETT
T bit set
SLEEP Transition to power-down mode
STBANK Register save to specified register bank entry
STC
Store control register data
STS
Store system register data
TRAPA Trap exception handling
Bit
10
manipulation
BAND
BCLR
Bit AND
Bit clear
BLD
Bit load
BOR
Bit OR
BSET
Bit set
BST
Bit store
BXOR
Bit exclusive OR
BANDNOT Bit NOT AND
BORNOT Bit NOT OR
BLDNOT Bit NOT load
Total:
91
No. of
Instructions
36
14
197
Rev. 3.00 Jun. 18, 2008 Page 52 of 1160
REJ09B0191-0300