SH7206 Datasheet, PDF (195/1188 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

Section 6 User Break Controller (UBC)
 Whether or not an access issued on the C bus by the CPU is issued on the I bus depends on
the cache settings. Regarding the I bus operation under cache conditions, see table 7.8 in
section 7, Cache.
 When a break condition is specified for the I bus, only the data access cycle is monitored.
The instruction fetch cycle (including the cache renewal cycle) is not monitored.
 The DMAC only issues data access cycles for I bus cycles.
 If a break condition is specified for the I bus, even when the condition matches in an I bus
cycle resulting from an instruction executed by the CPU, at which instruction the user
break interrupt request is to be accepted cannot be clearly defined.
Rev. 3.00 Jun. 18, 2008 Page 171 of 1160
REJ09B0191-0300