SH7206 Datasheet, PDF (191/1188 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

Section 6 User Break Controller (UBC)
6.3.6 Break Control Register (BRCR)
BRCR sets the following conditions:
1. Specifies whether a start of user break interrupt exception processing by instruction fetch cycle
is set before or after instruction execution.
2. Specifies the pulse width of the UBCTRG output when a break condition is satisfied.
BRCR is a 32-bit readable/writable register that has break condition match flags and bits for
setting other break conditions. For the condition match flags of bits 15 to 12, writing 1 is invalid
(previous values are retained) and writing 0 is only possible. To clear the flag, write 0 to the flag
bit to be cleared and 1 to all other flag bits. BRCR is initialized to H'00000000 by a power-on
reset, but retains its previous value by a manual reset or in software standby mode or sleep mode.
Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
-
-
-
-
-
-
-
-
-
-
-
-
-
-
CKS[1:0]
Initial value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: R R R R R R R R R R R R R R R/W R/W
Bit: 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
SCMFC SCMFC SCMFD SCMFD
0
1
0
1
-
-
-
-
- PCB1 PCB0 -
-
-
-
-
Initial value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: R/W R/W R/W R/W R R R R R R/W R/W R R R R R
Bit
Bit Name
31 to 18 
17, 16 CKS[1:0]
Initial
Value
All 0
00
R/W Description
R
Reserved
These bits are always read as 0. The write value
should always be 0.
R/W Clock Select
Specifies the pulse width output to the UBCTRG pin
when a break condition is satisfied.
00: Pulse width of UBCTRG is one bus clock cycle
01: Pulse width of UBCTRG is two bus clock cycles
10: Pulse width of UBCTRG is four bus clock cycles
11: Pulse width of UBCTRG is eight bus clock cycles
Rev. 3.00 Jun. 18, 2008 Page 167 of 1160
REJ09B0191-0300