SH7206 Datasheet, PDF (1010/1188 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

Section 22 Power-Down Modes
22.2.5 System Control Register 1 (SYSCR1)
SYSCR1 is an 8-bit readable/writable register that enables or disables access to the on-chip RAM.
SYSCR1 is initialized to H'FF by a power-on reset but retains its previous value by a manual reset
or in software standby mode. Only byte access is valid.
When an RAME bit is set to 1, the corresponding on-chip RAM area is enabled. When an RAME
bit is cleared to 0, the corresponding on-chip RAM area cannot be accessed. In this case, an
undefined value is returned when reading data or fetching an instruction from the on-chip RAM,
and writing to the on-chip RAM is ignored. The initial value of an RAME bit is 1.
Note that when clearing the RAME bit to 0 to disable the on-chip RAM, be sure to execute an
instruction to read from or write to the same arbitrary address in each page before setting the
RAME bit. If such an instruction is not executed, the data last written to each page may not be
written to the on-chip RAM. Furthermore, an instruction to access the on-chip RAM should not be
located immediately after the instruction to write to SYSCR1. If an on-chip RAM access
instruction is set, normal access is not guaranteed.
Note: See section 22.4, Usage Notes, when writing data to this register.
Bit: 7
6
5
4
3
2
1
0
-
-
-
- RAME3 RAME2 RAME1 RAME0
Initial value: 1
1
1
1
1
1
1
1
R/W: R
R
R
R R/W R/W R/W R/W
Bit
7 to 4
3
2
Bit Name

RAME3
RAME2
Initial
Value
All 1
1
1
R/W
R
R/W
R/W
Description
Reserved
These bits are always read as 1. The write value
should always be 1.
RAM Enable 3 (corresponding RAM addresses: Page
3 in on-chip RAM*)
0: On-chip RAM disabled
1: On-chip RAM enabled
RAM Enable 2 (corresponding RAM addresses: Page
2 in on-chip RAM*)
0: On-chip RAM disabled
1: On-chip RAM enabled
Rev. 3.00 Jun. 18, 2008 Page 986 of 1160
REJ09B0191-0300