SH7206 Datasheet, PDF (1166/1188 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

Item
Page Revision (See Manual for Details)
8.5.7 Burst ROM (Clocked
324 Figure amended.
Asynchronous) Interface
Figure 8.36 Burst ROM Access
Timing (Clocked Asynchronous)
CKIO
T1 Tw Tw T2B Twb T2B Twb T2B Twb T2
(Bus Width = 32 Bits, 16-Byte
Transfer (Number of Burst 4), Wait
Cycles Inserted in First Access =
2, Wait Cycles Inserted in Second
and Subsequent Access Cycles =
1)
8.5.12 Wait between Access
Cycles
Table 8.18 Conditions for
Determining Number of Idle
Cycles
345 Table amended.
Description of [5] Read data transfer cycle amended.
(Before) HM[1:0] bits →
(After) HW[1:0] bits
8.5.14 Others
352 Description amended.
(1) Reset
… All control registers are initialized. In software
standby, sleep, and …
9.3.4 DMA Channel Control
Registers (CHCR)
369 Description of bit 23 amended.
… This bit is valid only in level detection by CHCR_0 to
CHCR_3. …
371 Description of bit 17 amended.
Specifies whether DACK and TEND are output in data
read cycle or in data write cycle in dual address
mode.In single address mode, DACK and TEND are
always output regardless of the specification by this
bit.This bit is valid only in CHCR_0 to CHCR_3. This bit
is reserved in CHCR_4 to CHCR_7; it is always read as
0 and the write value should always be 0.
0: DACK and TEND are outputs in read cycle
(dual address mode)
1: DACK and TEND are outputs in write cycle
(dual address mode)
9.5 Usage Notes
407 Added
Rev. 3.00 Jun. 18, 2008 Page 1142 of 1160
REJ09B0191-0300