SH7206 Datasheet, PDF (378/1188 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

Section 8 Bus State Controller (BSC)
Changing the registers in the BSC while the write buffer is operating may disrupt correct write
access. Therefore, do not change the registers in the BSC immediately after a write access. If this
change becomes necessary, do it after executing a dummy read of the write data.
(3) On-Chip Peripheral Module Access
To access an on-chip module register, two or more peripheral module clock (Pφ) cycles are
required. Care must be taken in system design.
When the CPU writes data to the internal peripheral registers, the CPU performs the succeeding
instructions without waiting for the completion of writing to registers.
For example, a case is described here in which the system is transferring to the software standby
mode for power savings. To make this transition, the SLEEP instruction must be performed after
setting the STBY bit in the STBCR register to 1. However a dummy read of the STBCR register is
required before executing the SLEEP instruction. If a dummy read is omitted, the CPU executes
the SLEEP instruction before the STBY bit is set to 1, thus the system enters sleep mode not
software standby mode. A dummy read of the STBCR register is indispensable to complete
writing to the STBY bit.
To reflect the change by internal peripheral registers while performing the succeeding instructions,
execute a dummy read of registers to which write instruction is given and then perform the
succeeding instructions.
Rev. 3.00 Jun. 18, 2008 Page 354 of 1160
REJ09B0191-0300