SH7206 Datasheet, PDF (1169/1188 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

Item
Page Revision (See Manual for Details)
13.2.3 Compare Match Counter
(CMCNT)
704 Description amended.
… When the value in CMCNT and the value in
compare match constant register (CMCOR) match,
CMCNT is cleared to H'0000 and the CMF flag in
CMCSR is set to 1.
CMCNT is initialized to H'0000 when the corresponding
count start bit for a channel in the compare match timer
start register (CMSTR) is cleared from 1 to 0.
CMCNT is initialized to H'0000 by a power-on reset or
in software standby mode, but retains its previous value
in module standby mode.
14.3.2 Watchdog Timer
716
Control/Status Register (WTCSR)
Description amended.
Bit
2 to 0
Bit Name
CKS[2:0]
Initial
Value
000
R/W Description
R/W Clock Select
These bits select the clock to be used for the WTCNT
count from the eight types obtainable by dividing the
peripheral clock (Pf). The overflow period that is
shown inside the parenthesis in the table is the value
when the peripheral clock (Pf) is 33 MHz.
Bits 2 to 0
Clock Ratio
Overflow Cycle
000:
1 × Pφ
7.7 µs
001:
1/64 × Pφ
500 µs
010:
1/128 × Pφ
1.0 ms
011:
1/256 × Pφ
2.0 ms
100:
1/512 × Pφ
4.0 ms
101:
1/1024 × Pφ
8.0 ms
110:
1/4096 × Pφ
32 ms
111:
1/16384 × Pφ
128 ms
14.5.3 Interval Timer Overflow 725
Flag
14.5.4 System Reset by WDTOVF 726
Signal
Added
Section number amended.
14.5.5 Manual Reset in Watchdog 726 Section number amended.
Timer Mode
15.3.9 FIFO Control Register
(SCFCR)
758 Description of bit 3 amended.
Note: * Regardless of the input value, CTS level and
RTS level have no effect on the transmit
operation and the receive operation.
15.4.2 Operation in Asynchronous 776
Mode
(3) Transmitting and Receiving
Data
Description amended.
5. When modem control is enabled in channel 3, the
RTS signal is output according to the empty situation
of SCFRDR.
Rev. 3.00 Jun. 18, 2008 Page 1145 of 1160
REJ09B0191-0300