SH7206 Datasheet, PDF (25/1188 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

Section 1 Overview
Section 1 Overview
1.1 SH7206 Features
This LSI is a single-chip RISC (Reduced Instruction Set Computer) microprocessor that integrates
a Renesas Technology original RISC CPU core with peripheral functions required for system
configuration.
The CPU in this LSI has a RISC-type instruction set and uses a superscalar architecture and a
Harvard architecture, which greatly improves instruction execution speed. In addition, the 32-bit
internal-bus architecture enhances data processing power. With this CPU, it has become possible
to assemble low-cost, high-performance, and high-functioning systems, even for applications that
were previously impossible with microprocessors, such as realtime control, which demands high
speeds.
In addition, this LSI includes on-chip peripheral functions necessary for system configuration,
such as a cache, a large-capacity RAM, a direct memory access controller (DMAC), multi-
function timer pulse units 2 (MTU2 and MTU2S), a serial communication interface with FIFO
(SCIF), an A/D converter, a D/A converter, an interrupt controller (INTC), I/O ports, and I²C bus
interface 3 (IIC3).
This LSI also provides an external memory access support function to enable direct connection to
various memory devices or peripheral LSIs.
These on-chip functions significantly reduce costs of designing and manufacturing application
systems.
Furthermore, I/O pins in this LSI have weak keeper circuits that prevent the pin voltage from
entering an intermediate potential range. Therefore, no external circuits to fix the input level are
required, which reduces the parts number considerably.
The features of this LSI are listed in table 1.1.
Rev. 3.00 Jun. 18, 2008 Page 1 of 1160
REJ09B0191-0300