SH7206 Datasheet, PDF (1171/1188 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

Item
Page Revision (See Manual for Details)
16.6 Bit Synchronous Circuit
831 Figure replaced.
Figure 16.22 Bit Synchronous
Circuit Timing
Table 16.5 Time for Monitoring
SCL
832 Table amended, note*1 deleted.
CKS3
CKS2 Time for Monitoring SCL
0
0
9 tpcyc*
1
21 tpcyc*
1
0
33 tpcyc*
1
81 tpcyc*
Note : * tpcyc indicates the freguency of the peripheral
clock (Pφ).
16.7.1 Note on Issue of Stop/Start 833 Title added.
Conditions
16.7.2 Settings for Multi-Master 833 Added.
Operation
16.7.3 Note on Master Receive 833 Added.
Mode
16.7.4 Note on Setting ACKBT in 834 Added.
Master Receive Mode
16.7.5 Note on the States of Bits 834
MST and TRN when Arbitration is
Lost
Added.
17.1 Features
836 Figure amended.
Figure 17.1 Block Diagram of A/D
Converter
ADC0
AVCC
AVref
AVSS
10-bit
D/A
ADC1
AVCC
AVref
AVSS
10-bit
D/A
Rev. 3.00 Jun. 18, 2008 Page 1147 of 1160
REJ09B0191-0300