SH7206 Datasheet, PDF (1138/1188 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

Section 25 Electrical Characteristics
Tpcm0 Tpcm0w Tpcm1 Tpcm1w Tpcm1w Tpcm1w Tpcm1w Tpcm2 Tpcm2w
CKIO
A25 to A0
CExx
RD/WR
ICIORD
Read
D15 to D0
Write
ICIOWR
D15 to D0
BS
t_AD1
t_CSD1
t_RWD1
t_WDD1
t_BSD
t_BSD
t_ICRSD
t_ICWSD
t_AD1
t_CSD1
t_RWD1
t_ICRSD
t_RDH1
t_RDS1
t_ICWSD
t_WDH1
DACKn
TENDn*
t_DACD
WAIT
t_WTH
t_WTS
t_WTH
t_WTS
t_DACD
Note: * The waveform for DACKn and TENDn is when active low is specified.
Figure 25.43 PCMCIA I/O Card Bus Cycle
(TED = 2 Cycles, TEH = 1 Cycle, Software Wait Cycle 0, Hardware Wait Cycle 1)
Rev. 3.00 Jun. 18, 2008 Page 1114 of 1160
REJ09B0191-0300