SH7206 Datasheet, PDF (708/1188 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

Section 12 Port Output Enable 2 (POE2)
Initial
Bit
Bit Name Value
12
POE8F 0
11, 10 
All 0
9
POE8E 0
8
PIE3
0
7 to 2 
All 0
R/W Description
R/(W)*¹ POE8 Flag
Indicates that a high impedance request has been input
to the POE8 pin.
[Clearing conditions]
• By writing 0 to POE8F after reading POE8F = 1
(when the falling edge is selected by bits 1 and 0 in
ICSR3)
• By writing 0 to POE8F after reading POE8F = 1 after
a high level input to POE8 is sampled at Pφ/8, Pφ/16,
or Pφ/128 clock (when low-level sampling is selected
by bits 1 and 0 in ICSR3)
[Setting condition]
• When the input condition set by bits 1 and 0 in
ICSR3 occurs at the POE8 pin
R
Reserved
These bits are always read as 0. The write value should
always be 0.
R/W*² POE8 High-Impedance Enable
Specifies whether to place the pins in high-impedance
state when the POE8F bit in ICSR3 is set
to 1.
0: Does not place the pins in high-impedance state
1: Places the pins in high-impedance state
R/W Port Interrupt Enable 3
Enables or disables interrupt requests when the POE8
bit in ICSR3 is set to 1.
0: Interrupt requests disabled
1: Interrupt requests enabled
R
Reserved
These bits are always read as 0. The write value should
always be 0.
Rev. 3.00 Jun. 18, 2008 Page 684 of 1160
REJ09B0191-0300