SH7206 Datasheet, PDF (762/1188 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

Section 15 Serial Communication Interface with FIFO (SCIF)
Initial
Bit
Bit Name Value R/W Description
6
RIE
0
R/W Receive Interrupt Enable
Enables or disables the receive FIFO data full (RXI)
interrupts requested when the RDF flag or DR flag in
serial status register (SCFSR) is set to1, receive-error
(ERI) interrupts requested when the ER flag in SCFSR
is set to1, and break (BRI) interrupts requested when
the BRK flag in SCFSR or the ORER flag in line status
register (SCLSR) is set to1.
0: Receive FIFO data full interrupt (RXI), receive-error
interrupt (ERI), and break interrupt (BRI) requests
are disabled
1: Receive FIFO data full interrupt (RXI), receive-error
interrupt (ERI), and break interrupt (BRI) requests
are enabled*
Note: * RXI interrupt requests can be cleared by
reading the DR or RDF flag after it has been
set to 1, then clearing the flag to 0, or by
clearing RIE to 0. ERI or BRI interrupt requests
can be cleared by reading the ER, BR or
ORER flag after it has been set to 1, then
clearing the flag to 0, or by clearing RIE and
REIE to 0.
5
TE
0
R/W Transmit Enable
Enables or disables the serial transmitter.
0: Transmitter disabled
1: Transmitter enabled*
Note: * Serial transmission starts after writing of
transmit data into SCFTDR. Select the transmit
format in SCSMR and SCFCR and reset the
transmit FIFO before setting TE to 1.
Rev. 3.00 Jun. 18, 2008 Page 738 of 1160
REJ09B0191-0300