SH7206 Datasheet, PDF (94/1188 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

Section 3 Clock Pulse Generator (CPG)
Figure 3.1 shows a block diagram of the clock pulse generator.
CKIO
XTAL
EXTAL
Crystal
oscillator
On-chip oscillator
PLL circuit 1
(×1, 2, 3, 4, 6, 8)
PLL circuit 2
(×4)
Divider 2
×1
×1/2
×1/3
×1/4
Divider 1
×1
×1/2
×1/3
×1/4
×1/6
×1/8
×1/12
MTU clock
(Mφ, Max. 100 MHz)
Internal clock
(Iφ, Max. 200 MHz)
Bus clock
(Bφ = CKIO, Max. 66.67 MHz)
Peripheral clock
(Pφ, Max. 33.33 MHz)
MD_CLK2
MD_CLK0
CPG control unit
Clock frequency
control circuit
Standby control circuit
FRQCR MCLKCR
STBCR STBCR2 STBCR3 STBCR4
Bus interface
[Legend]
FRQCR: Frequency control register
MCLKCR: MTU clock frequency control register
STBCR: Standby control register
STBCR2: Standby control register 2
STBCR3: Standby control register 3
STBCR4: Standby control register 4
Peripheral bus
Figure 3.1 Block Diagram of Clock Pulse Generator
Rev. 3.00 Jun. 18, 2008 Page 70 of 1160
REJ09B0191-0300