SH7206 Datasheet, PDF (863/1188 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

Section 17 A/D Converter (ADC)
17.3.1 A/D Data Registers A to H (ADDRA to ADDRH)
The sixteen A/D data registers, ADDRA_0 to ADDRH_0 (A/D0) and ADDRA_1 to ADDRH_1
(A/D1), are 16-bit read-only registers that store the results of A/D conversion.
An A/D conversion produces 10-bit data, which is transferred for storage into the ADDR
corresponding to the selected channel. The 10 bits of the result are stored in the upper bits (bits 15
to 6) of ADDR. Bits 5 to 0 of ADDR are reserved bits that are always read as 0.
Access to ADDR in 8-bit units is prohibited. ADDR must always be accessed in 16-bit units.
ADDR is initialized to H'0000 by a power-on reset or in software standby mode or module
standby mode.
Table 17.3 indicates the pairings of analog input channels and ADDR.
Bit: 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
-
-
-
-
-
-
Initial value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
Bit
15 to 6
5 to 0
Bit Name

Initial
Value R/W
All 0
R
All 0
R
Description
Bit data (10 bits)
Reserved
These bits are always read as 0. The write value
should always be 0.
Rev. 3.00 Jun. 18, 2008 Page 839 of 1160
REJ09B0191-0300