SH7206 Datasheet, PDF (130/1188 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

Section 4 Exception Handling
4.7 When Exception Sources Are Not Accepted
When an address error, register bank error (overflow), or interrupt is generated immediately after a
delayed branch instruction, it is sometimes not accepted immediately but stored instead, as shown
in table 4.11. When this happens, it will be accepted when an instruction that can accept the
exception is decoded.
Table 4.11 Exception Source Generation Immediately after Delayed Branch Instruction
Exception Source
Point of Occurrence
Address Error
Register Bank Error
(Overflow)
Interrupt
Immediately after a delayed Not accepted
branch instruction^*
Not accepted
Not accepted
Note: * Delayed branch instructions: JMP, JSR, BRA, BSR, RTS, RTE, BF/S, BT/S, BSRF,
BRAF
Rev. 3.00 Jun. 18, 2008 Page 106 of 1160
REJ09B0191-0300