SH7206 Datasheet, PDF (1143/1188 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

Section 25 Electrical Characteristics
25.4.9 SCIF Module Timing
Table 25.14 SCIF Module Timing
Conditions: PV_CC = 3.0 V to 3.6 V, V_CC = 1.15 V to 1.35 V, AV_CC = 3.0 V to 3.6 V,
V_SS = PV_SS = AV_SS = 0 V, Ta = −20°C to +85°C
Item
Symbol Min.
Input clock cycle (clocked synchronous) t
12
Scyc
(asynchronous)
4
Input clock rise time
Input clock fall time
Input clock width
Transmit data delay time
(clocked synchronous)
t
—
SCKr
t_SCKf
—
t_SCKW
0.4
t_TXD
—
Receive data setup time
(clocked synchronous)
t
RXS
4t
pcyc
+
15
Receive data hold time
(clocked synchronous)
t
RXH
1t
pcyc
+
15
Note: t_pcyc indicates peripheral clock (Pφ) cycle.
Max.
—
—
1.5
1.5
0.6
3t_pcyc + 15
—
—
Unit
t
pcyc
t_pcyc
t
pcyc
t_pcyc
t_Scyc
ns
ns
ns
Figure
Figure 25.51
Figure 25.52
SCK
t_SCKW
t_SCKr
t_Scyc
t_SCKf
Figure 25.51 SCK Input Clock Timing
SCK
(input/output)
TxD
(data transmit)
RxD
(data receive)
t_Scyc
t_TXD
t_RXS t_RXH
Figure 25.52 SCIF Input/Output Timing in Clocked Synchronous Mode
Rev. 3.00 Jun. 18, 2008 Page 1119 of 1160
REJ09B0191-0300