SH7206 Datasheet, PDF (167/1188 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

Section 5 Interrupt Controller (INTC)
5.7 Interrupt Response Time
Table 5.5 lists the interrupt response time, which is the time from the occurrence of an interrupt
request until the interrupt exception handling starts and fetching of the first instruction in the
exception service routine begins. The interrupt processing operations differ in the cases when
banking is disabled, when banking is enabled without register bank overflow, and when banking is
enabled with register bank overflow. Figures 5.4 and 5.5 show examples of pipeline operation
when banking is disabled. Figures 5.6 and 5.7 show examples of pipeline operation when banking
is enabled without register bank overflow. Figures 5.8 and 5.9 show examples of pipeline
operation when banking is enabled with register bank overflow.
Table 5.5 Interrupt Response Time
Number of States
Item
NMI
User Break
Time from occurrence of interrupt
request until interrupt controller
identifies priority, compares it with
mask bits in SR, and sends interrupt
request signal to CPU
2 Icyc +
2 Bcyc +
1 Pcyc
3 Icyc
Time from
No register
input of
banking
interrupt
request signal
to CPU until
sequence
currently being
Register
executed is
banking
completed,
without
interrupt
register
exception
bank
handling starts,
overflow
and first
instruction in Register
interrupt
banking
exception
with
service routine register
is fetched
bank
overflow
Min.
Max.
Min.
Max.
Min.
Max.
3 Icyc + m1 + m2
4 Icyc + 2(m1 + m2) + m3




H-UDI
2 Icyc +
1 Pcyc
IRQ, PINT
2 Icyc +
3 Bcyc +
1 Pcyc
3 Icyc + m1 + m2
12 Icyc + m1 + m2
3 Icyc + m1 + m2
3 Icyc + m1 + m2 + 19(m4)
Peripheral
Module
2 Icyc +
1 Bcyc +
1 Pcyc
Remarks
Min. is when the interrupt
wait time is zero.
Max. is when a higher-
priority interrupt request has
occurred during interrupt
exception handling.
Min. is when the interrupt
wait time is zero.
Max. is when an interrupt
request has occurred during
execution of the RESBANK
instruction.
Min. is when the interrupt
wait time is zero.
Max. is when an interrupt
request has occurred during
execution of the RESBANK
instruction.
Rev. 3.00 Jun. 18, 2008 Page 143 of 1160
REJ09B0191-0300