SH7206 Datasheet, PDF (7/1188 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

• Examples
The notation used for register names, bit names, numbers, and symbols in this manual is
described below.
(1) Registers
The style (register name)_(channel number) is used in cases where the same or a
similar function is implemented on more than one channel.
Example: CMCSR_0
(2) Bits
When bit names are given in this manual, the higher-order bits are to the left and the
lower-order bits are to the right.
Example: CKS1, CKS0
(3) Numbers
Binary numbers are given as B'xxxx, hexadecimal are given as H'xxxx, and decimal
are given as xxxx.
Examples: B'11 or 11, H'EFA0, 1234
(4) Symbols
An overbar is added to the names of active-low signals.
Example: WDTOVF
(4)
(1)
14.2.2 Compare Match Control/Status Register_0, _1 (CMCSR_0, CMCSR_1)
CMCSR indicates compare match generation, enables or disables interrupts, and selects the counter
input clock.Generation of a WDTOVF signal or interrupt initializes the TCNT value to 0.
14.3 Operation
14.3.1 Interval Count Operation
When an internal clock is selected with the CKS1 and CKS0 bits in CMCSR and the STR bit in
CMSTR is set to 1, CMCNT starts incrementing using the selected clock. When the values in
CMCNT and the compare match constant register (CMCOR) match, CMCNT is cleared to H'0000
and the CMF flag in CMCSR is set to 1. When the CKS1 and CKS0 bits are set to B'01 at this time,
a f/4 clock is selected.
Rev. 0.50, 10/04, page 416 of 914
(2)
(3)
Note: The bit names and sentences in the above figure are examples, and have nothing to do
with the contents of this manual.
Rev. 3.00 Jun. 18, 2008 Page vii of xxiv