SH7206 Datasheet, PDF (225/1188 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

Figure 8.1 shows a block diagram of the BSC.
Section 8 Bus State Controller (BSC)
BREQ
BACK
WAIT
Bus
mastership
controller
Wait
controller
CMNCR
CS0WCR
CS8WCR
CS0 to CS8
MD2, MD0
Area
controller
CS0BCR
CS8BCR
A25 to A0,
D31 to D0
BS, RD/WR,
RD, WE3 to WE0,
RASU, RASL,
CASU, CASL
CKE, DQMxx, AH,
FRAME,
CE2A, CE2B
REFOUT
Memory
controller
Refresh
controller
SDCR
RTCSR
RTCNT
Comparator
RTCOR
[Legend]
CMNCR: Common control register
CSnWCR: CSn space wait control register (n = 0 to 8)
CSnBCR: CSn space bus control register (n = 0 to 8)
SDCR: SDRAM control register
RTCSR: Refresh timer control/status register
RTCNT: Refresh timer counter
RTCOR: Refresh time constant register
BSC
Figure 8.1 Block Diagram of BSC
Rev. 3.00 Jun. 18, 2008 Page 201 of 1160
REJ09B0191-0300